1. Field of the Invention
This invention relates to a phase-locked loop with two negative feedback loops. The outer negative feedback loop is a conventional PLL loop. The inner negative feedback loop consists of a voltage controlled oscillator (VCO) and a frequency voltage converter (FVC) is inside a conventional outer PLL loop. The inclusion of the inner negative feedback loop of a VCO and an FVC improves the phase noise characteristic and the stability of PLL.
2. Description of the Related Art
Phase-locked loops (PLLs) have become ubiquitous in modern communication systems and integrated chips because of their versatility. Phase-locked loops (PLLs) have been used popularly such as frequency multiplication synthesis for communication system, and high frequency clock signal for integrated digital chips.
FIG. 1 is a block diagram showing the structure of the conventional phase-locked loop.
As shown in FIG. 1, the phase-locked loop (PLL) comprises a phase frequency detector (PFD) (10) comparing the phase difference between the given input signal to the PLL and the feedback signal, and outputting up or down signal based on the phase difference, a charge pump (CP) (20) outputting the current proportional to the up and down signals outputted from the phase frequency detector (10); a loop filter (LPF) (30) outputting the voltage by filtering the current outputted from the charge pump (20); a voltage-controlled oscillator (40) outputting the frequency based on the voltage outputted from the loop filter (30); a divider (50) dividing the frequency outputted from the voltage-controlled oscillator (40) and feedbacking to the phase frequency detector (10); and changes the frequency depending on the signal which is inputted into PLL.
This typical PLL reduces the jitter in the output clock signal or suppresses the phase noise in the output signal by filtering the high frequency jitter or phase noise components in the authorized reference clock (or input clock).
The phase-locked loops (PLLs) have been widely used as frequency multipliers in communication systems and high frequency clock signal generators in integrated digital chips. The voltage-controlled oscillator (VCO) is an oscillator circuit for obtaining the desired frequency output by controlling its input voltage.
At this point, the voltage-controlled oscillator (VCO) (40) in the PLL is a circuit for generating a specific frequency by the control voltage. Commonly used oscillators are an LC VCO or a ring VCO.
The LC VCO is suitable for communication systems because it is superior to the ring VCO in terms of noise characteristics. However, in the standard CMOS process, a bulky inductor is expensive because it is not a standard device yet requires a large area.
On the other hand, a ring oscillator is suitable for clock signal generation used in digital chips because it occupies small area. That is, a ring oscillator can be used in circuits having no strict requirement regarding the phase noise characteristics, and can be easily made by the standard CMOS process. Moreover, a ring oscillator has a wide frequency range.
When a ring-type oscillator or LC VCO is used in a phase-locked loop, commonly used method of suppressing VOC noise of a phase-locked loop is to have a wide bandwidth. However, the large bandwidth cannot suppress other block's noise which has a low-pass transfer characteristic.